Network Technologies, AFC, Phase I
Continuous Time Spiking Neural Network Field Programmable Neural Network Array
Objective
To develop a continuous time, mixed signal, programmable spiking neural network array integrated circuit.
Description
Field programmable gate arrays (FPGA) are a high volume, programmable, relatively low cost, approach for creating hardware applications from state machines to softcore processors. A field programmable neural network equivalent of a FPGA is needed to provide the same level of flexibility at low cost for neural network applications. A field programmable neural network array would also provide bring FPGA-like functionality to DoD and Army neural network applications and empower future neural network developments.
Spiking neural networks are analog and asynchronous in nature [1]-[5]. A new subfield of signal processing, continuous time (CT) systems, offers a hybrid of analog and digital [12]-[17]. CT is asynchronous like analog signal processing with the benefits of discrete voltage levels from digital signal processing. CT offers unique advantages for working with hybrid, mixed mode (analog and digital) systems.
Field programmable analog arrays (FPAA) offer analog gain blocks, programmable filters and comparators [6]. With analog memory elements (like memristors, ferroelectric capacitors, flash/FET transistors, etc) FPAA arrays could be expanded to create programmable neural network blocks. Continuous time digital signal processing offers an analog/digital hybrid signal processing mode which fits well with spiking neural network signal flows.
Phase I
Offeror shall research the feasibility of developing a continuous time [14]-[17] programmable spiking neural network using analog memory, FPGA, and FPAA. Offeror shall research the feasibility of creating an integrated circuit based on analog memory, FPGA, and FPAA. Offeror shall research the feasibility of applying the system towards real-time, streaming, signal processing applications. Offeror shall research the feasibility of creating analog compute [7]-[9] in memory macro cells.
Offeror shall propose a programmable design with programmable features similar to FPGA and FPAA. Offeror shall propose a list of selectable neural network functions, such as: non-linear activation functions, analog signal processing functions (multiplication, addition, subtraction, and log, etc), convolutional neural networks, pooling, etc. Offer may create models, simulations, etc to illustrate potential capabilities. Offeror shall provide a hardware/software/programming system architecture report.
Phase II
- Offeror shall develop a “Continuous Time Spiking Neural Network Field Programmable Neural Network Array” based on Phase I effort and Phase II research proposal.
- Offer shall prototype a continuous time [14]-[17] programmable spiking neural network using analog memory, FPGA, and FPAA.
- Offer shall select a test case (for example: an Analog Spiking Neural Network Based Phase Detector in [3], real-time electrocardiogram signals based on [10]-[11], etc.) and compare prototype analog memory, FPGA, and FPAA implementation to conventional FPGA neural network, and conventional software based neural network. Recommended metrics include: FPGA/FPAA floor plan resources, power, parallelism, lines of code, latency and accuracy.
- Offeror shall propose a Future of Vertical Flight/UAS demonstration project with government concurrence for the Phase II development effort.
- Offeror shall deliver to the government point of contact for test and evaluation: 1 prototype “Continuous Time Spiking Neural Network Field Programmable Neural Network Array” system. Offeror shall provide 2 days of virtual training for the system.
- Offeror shall design a continuous time system, field programmable neural network array integrated circuit based on the phase II effort. Offer shall simulate IC design to demonstrate potential capabilities for field programmable neural network IC design.
- Offer shall provide year 1 and year 2 project reports.
Phase III
Offeror shall fabricate Continuous Time Spiking Neural Network Field Programable Neural Network Array integrated circuit. Offeror shall commercialize Continuous Time Spiking Neural Network Field Programmable Neural Network Array for both government and commercial application spaces. Offeror will integrate neural network array into a Future of Vertical Lift Army Aviation application or Missile subsystem currently under development or via technology refresh. Offeror will apply neural network array IC to automotive vision applications, medical electronics applications, or big data analytics.
Submission Information
For more information, and to submit your full proposal package, visit the DSIP Portal.
SBIR|STTR Help Desk: usarmy.sbirsttr@army.mil
References:
- H. Jang, et al.; “An introduction to probabilistic Spiking Neural Networks: Probabilstic Models, Learning Rules, and Applications” in IEEE Signal Processing Magazine, vol 36, no.6, pp. 64-77, Nov 2019, doi: 10.1109/MSP.2019.2935234+9;
- K. Yamazaki, et al.: “Spiking Neural Networks and Their Applications: A Review,” Brain Sci. 2022, 12(7), 863;
- H. Lehmann, et al. “Analog Spiking Neural Network Based Phase Detector,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4837-4846, Dec. 2022, doi: 10.1109/TCSI.2022.3204433;
- H. Lehmann, et al. “Direct Signal Encoding With Analog Resonate-and-Fire Neurons,” in IEEE Access, vol. 11, pp. 50052-50063, 2023, doi: 10.1109/ACCESS.2023.3278098;
- S. Uenohara and K. Aihara, “A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain,” in IEEE Access, vol. 10, pp. 48338-48348, 2022, doi: 10.1109/ACCESS.2022.3170579.;
- J. Hasler, “Large-Scale Field-Programmable Analog Arrays,” in Proceedings of the IEEE, vol. 108, no. 8, pp. 1283-1302, Aug. 2020, doi: 10.1109/JPROC.2019.2950173;
- G. W. Burr, S. Ambrogio, P. Narayanan, H. Tsai, C. Mackin and A. Chen, “Accelerating Deep Neural Networks with Analog Memory Devices,” 2019 China Semiconductor Technology International Conference (CSTIC), Shanghai, China, 2019, pp. 1-3, doi: 10.1109/CSTIC.2019.8755642;
- O. Fujita and Y. Amemiya, “A floating-gate analog memory device for neural networks,” in IEEE Transactions on Electron Devices, vol. 40, no. 11, pp. 2029-2035, Nov. 1993, doi: 10.1109/16.239745;
- N. Laubeuf, “Analog Compute in Memory and Breaking Digital Number Representations,” 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, 2022, pp. 1-2, doi: 10.1109/VLSI-SoC54400.2022.9939611.;
- S. Qaisar and S. Hussain: “Arrhythmia Diagnosis by Using Level-Crossing ECG Sampling and Sub-Bands Features Extraction for Mobile Healthcare,” Sensors, Vol. 20, Issue 8, pp. 2252, 2020;
- A. Goldberger, et al.: PhysioBank, PhysioToolkit, and PhysioNet: Components of a new research resource for complex physiologic signals, Circulation [Online], Vol 101, Issue 23, pp. e215–e220, 2000;
- A. Antony, et al.: “Asynchronous Adaptive Threshold Level Crossing ADC for Wearable ECG Sensors,” J Med Syst 43, 78 (2019).;
- Y. Tsividis, “Continuous-time digital signal processing,” Electronics Letters 39(21), 1551 (2003).;
- Y. Tsividis, “Event-Driven Data Acquisition and Digital Signal Processing—A Tutorial”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 8 (2010).;
- M. Kurchuk, Signal Encoding and Digital Signal Processing in Continuous Time, Dissertation, Columbia University, 2011;
- C. Vezyrtzis and Y. Tsividis, “Processing of signals using level-crossing sampling,” Jun. 2009, pp. 2293–2296. doi:10.1109/ISCAS.2009.5118257;
- P. Jungwirth and W. M. Crowe: “Continuous Time Digital Signal Processing and Signal Reconstruction,” IEEE Annual Computing and Communication Workshop and Conference (CCWC), pp. 1205-1211, Las Vegas, NV, USA, 2023. doi: 10.1109/CCWC57344.2023.10099213;
- B. Rajendran, A. Sebastian, M. Schmuker, N. Srinivasa and E. Eleftheriou, “Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches,” in IEEE Signal Processing Magazine, vol. 36, no. 6, pp. 97-110, Nov. 2019, doi: 10.1109/MSP.2019.2933719
Objective
To develop a continuous time, mixed signal, programmable spiking neural network array integrated circuit.
Description
Field programmable gate arrays (FPGA) are a high volume, programmable, relatively low cost, approach for creating hardware applications from state machines to softcore processors. A field programmable neural network equivalent of a FPGA is needed to provide the same level of flexibility at low cost for neural network applications. A field programmable neural network array would also provide bring FPGA-like functionality to DoD and Army neural network applications and empower future neural network developments.
Spiking neural networks are analog and asynchronous in nature [1]-[5]. A new subfield of signal processing, continuous time (CT) systems, offers a hybrid of analog and digital [12]-[17]. CT is asynchronous like analog signal processing with the benefits of discrete voltage levels from digital signal processing. CT offers unique advantages for working with hybrid, mixed mode (analog and digital) systems.
Field programmable analog arrays (FPAA) offer analog gain blocks, programmable filters and comparators [6]. With analog memory elements (like memristors, ferroelectric capacitors, flash/FET transistors, etc) FPAA arrays could be expanded to create programmable neural network blocks. Continuous time digital signal processing offers an analog/digital hybrid signal processing mode which fits well with spiking neural network signal flows.
Phase I
Offeror shall research the feasibility of developing a continuous time [14]-[17] programmable spiking neural network using analog memory, FPGA, and FPAA. Offeror shall research the feasibility of creating an integrated circuit based on analog memory, FPGA, and FPAA. Offeror shall research the feasibility of applying the system towards real-time, streaming, signal processing applications. Offeror shall research the feasibility of creating analog compute [7]-[9] in memory macro cells.
Offeror shall propose a programmable design with programmable features similar to FPGA and FPAA. Offeror shall propose a list of selectable neural network functions, such as: non-linear activation functions, analog signal processing functions (multiplication, addition, subtraction, and log, etc), convolutional neural networks, pooling, etc. Offer may create models, simulations, etc to illustrate potential capabilities. Offeror shall provide a hardware/software/programming system architecture report.
Phase II
- Offeror shall develop a “Continuous Time Spiking Neural Network Field Programmable Neural Network Array” based on Phase I effort and Phase II research proposal.
- Offer shall prototype a continuous time [14]-[17] programmable spiking neural network using analog memory, FPGA, and FPAA.
- Offer shall select a test case (for example: an Analog Spiking Neural Network Based Phase Detector in [3], real-time electrocardiogram signals based on [10]-[11], etc.) and compare prototype analog memory, FPGA, and FPAA implementation to conventional FPGA neural network, and conventional software based neural network. Recommended metrics include: FPGA/FPAA floor plan resources, power, parallelism, lines of code, latency and accuracy.
- Offeror shall propose a Future of Vertical Flight/UAS demonstration project with government concurrence for the Phase II development effort.
- Offeror shall deliver to the government point of contact for test and evaluation: 1 prototype “Continuous Time Spiking Neural Network Field Programmable Neural Network Array” system. Offeror shall provide 2 days of virtual training for the system.
- Offeror shall design a continuous time system, field programmable neural network array integrated circuit based on the phase II effort. Offer shall simulate IC design to demonstrate potential capabilities for field programmable neural network IC design.
- Offer shall provide year 1 and year 2 project reports.
Phase III
Offeror shall fabricate Continuous Time Spiking Neural Network Field Programable Neural Network Array integrated circuit. Offeror shall commercialize Continuous Time Spiking Neural Network Field Programmable Neural Network Array for both government and commercial application spaces. Offeror will integrate neural network array into a Future of Vertical Lift Army Aviation application or Missile subsystem currently under development or via technology refresh. Offeror will apply neural network array IC to automotive vision applications, medical electronics applications, or big data analytics.
Submission Information
For more information, and to submit your full proposal package, visit the DSIP Portal.
SBIR|STTR Help Desk: usarmy.sbirsttr@army.mil
References:
- H. Jang, et al.; “An introduction to probabilistic Spiking Neural Networks: Probabilstic Models, Learning Rules, and Applications” in IEEE Signal Processing Magazine, vol 36, no.6, pp. 64-77, Nov 2019, doi: 10.1109/MSP.2019.2935234+9;
- K. Yamazaki, et al.: “Spiking Neural Networks and Their Applications: A Review,” Brain Sci. 2022, 12(7), 863;
- H. Lehmann, et al. “Analog Spiking Neural Network Based Phase Detector,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4837-4846, Dec. 2022, doi: 10.1109/TCSI.2022.3204433;
- H. Lehmann, et al. “Direct Signal Encoding With Analog Resonate-and-Fire Neurons,” in IEEE Access, vol. 11, pp. 50052-50063, 2023, doi: 10.1109/ACCESS.2023.3278098;
- S. Uenohara and K. Aihara, “A 18.7 TOPS/W Mixed-Signal Spiking Neural Network Processor With 8-bit Synaptic Weight On-Chip Learning That Operates in the Continuous-Time Domain,” in IEEE Access, vol. 10, pp. 48338-48348, 2022, doi: 10.1109/ACCESS.2022.3170579.;
- J. Hasler, “Large-Scale Field-Programmable Analog Arrays,” in Proceedings of the IEEE, vol. 108, no. 8, pp. 1283-1302, Aug. 2020, doi: 10.1109/JPROC.2019.2950173;
- G. W. Burr, S. Ambrogio, P. Narayanan, H. Tsai, C. Mackin and A. Chen, “Accelerating Deep Neural Networks with Analog Memory Devices,” 2019 China Semiconductor Technology International Conference (CSTIC), Shanghai, China, 2019, pp. 1-3, doi: 10.1109/CSTIC.2019.8755642;
- O. Fujita and Y. Amemiya, “A floating-gate analog memory device for neural networks,” in IEEE Transactions on Electron Devices, vol. 40, no. 11, pp. 2029-2035, Nov. 1993, doi: 10.1109/16.239745;
- N. Laubeuf, “Analog Compute in Memory and Breaking Digital Number Representations,” 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, 2022, pp. 1-2, doi: 10.1109/VLSI-SoC54400.2022.9939611.;
- S. Qaisar and S. Hussain: “Arrhythmia Diagnosis by Using Level-Crossing ECG Sampling and Sub-Bands Features Extraction for Mobile Healthcare,” Sensors, Vol. 20, Issue 8, pp. 2252, 2020;
- A. Goldberger, et al.: PhysioBank, PhysioToolkit, and PhysioNet: Components of a new research resource for complex physiologic signals, Circulation [Online], Vol 101, Issue 23, pp. e215–e220, 2000;
- A. Antony, et al.: “Asynchronous Adaptive Threshold Level Crossing ADC for Wearable ECG Sensors,” J Med Syst 43, 78 (2019).;
- Y. Tsividis, “Continuous-time digital signal processing,” Electronics Letters 39(21), 1551 (2003).;
- Y. Tsividis, “Event-Driven Data Acquisition and Digital Signal Processing—A Tutorial”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 57, No. 8 (2010).;
- M. Kurchuk, Signal Encoding and Digital Signal Processing in Continuous Time, Dissertation, Columbia University, 2011;
- C. Vezyrtzis and Y. Tsividis, “Processing of signals using level-crossing sampling,” Jun. 2009, pp. 2293–2296. doi:10.1109/ISCAS.2009.5118257;
- P. Jungwirth and W. M. Crowe: “Continuous Time Digital Signal Processing and Signal Reconstruction,” IEEE Annual Computing and Communication Workshop and Conference (CCWC), pp. 1205-1211, Las Vegas, NV, USA, 2023. doi: 10.1109/CCWC57344.2023.10099213;
- B. Rajendran, A. Sebastian, M. Schmuker, N. Srinivasa and E. Eleftheriou, “Low-Power Neuromorphic Hardware for Signal Processing Applications: A Review of Architectural and System-Level Design Approaches,” in IEEE Signal Processing Magazine, vol. 36, no. 6, pp. 97-110, Nov. 2019, doi: 10.1109/MSP.2019.2933719