

Objective
This topic seeks to build an intellectual property (IP) library of designed, fabricated, and verified circuit blocks that can be licensed for use in future ROIC designs and de-bug the process design kit (PDK) to vastly reduce program risk for future DoD and commercial designs.
Description
This topic accepts Phase I proposals submissions for a cost up to $250,000 for a 6-month period of performance.
Most imaging sensor read-out integrated circuits (ROIC) for DoD use are fabricated in decades-old 180 nm semiconductor processes. This presents an obsolesce risk and forces ROIC designers to make undesirable trade-offs when trying to meet program specifications.
However, moving to a more advanced node like 90 or 65 nm presents an elevated risk because designers do not have any known good circuit building block IP and bugs may exist in the semiconductor fabricators’ process design kits (PDK) used by designers.
Phase I
Work with stakeholders to identify priority circuit blocks (those with most demand/ most universally useful, highest risk). Complete high-level design of selected circuit blocks.
Phase II
The design phase of the program could be accelerated to provide a knowledge transition in time even for a standard program, but the long lead time of fabrication would likely prevent circuit verification in time for initial transitions to the PM in this case. All the circuit blocks which could potentially be designed in this proposed effort exist in some form currently, and many companies have experience and IP that is directly applicable and can be leveraged.
Much of this IP has been generated on past SBIR programs, like those listed in Section 1, Part 5a. By moving to a new fabrication node, it is expected that additional capabilities can be realized (i.e., the circuit block performs measurably better in some way), the circuit can be implemented in a smaller area, it can do the same job with lower power, or all three. Most major risks associated with moving to a new node will need to be solved during simulation and verification steps in phase II.
Phase III
Submission Information
For more information, and to submit your full proposal package, visit the DSIP Portal.
SBIR|STTR Help Desk: usarmy.sbirsttr@army.mil
References:
Objective
This topic seeks to build an intellectual property (IP) library of designed, fabricated, and verified circuit blocks that can be licensed for use in future ROIC designs and de-bug the process design kit (PDK) to vastly reduce program risk for future DoD and commercial designs.
Description
This topic accepts Phase I proposals submissions for a cost up to $250,000 for a 6-month period of performance.
Most imaging sensor read-out integrated circuits (ROIC) for DoD use are fabricated in decades-old 180 nm semiconductor processes. This presents an obsolesce risk and forces ROIC designers to make undesirable trade-offs when trying to meet program specifications.
However, moving to a more advanced node like 90 or 65 nm presents an elevated risk because designers do not have any known good circuit building block IP and bugs may exist in the semiconductor fabricators’ process design kits (PDK) used by designers.
Phase I
Work with stakeholders to identify priority circuit blocks (those with most demand/ most universally useful, highest risk). Complete high-level design of selected circuit blocks.
Phase II
The design phase of the program could be accelerated to provide a knowledge transition in time even for a standard program, but the long lead time of fabrication would likely prevent circuit verification in time for initial transitions to the PM in this case. All the circuit blocks which could potentially be designed in this proposed effort exist in some form currently, and many companies have experience and IP that is directly applicable and can be leveraged.
Much of this IP has been generated on past SBIR programs, like those listed in Section 1, Part 5a. By moving to a new fabrication node, it is expected that additional capabilities can be realized (i.e., the circuit block performs measurably better in some way), the circuit can be implemented in a smaller area, it can do the same job with lower power, or all three. Most major risks associated with moving to a new node will need to be solved during simulation and verification steps in phase II.
Phase III
Submission Information
For more information, and to submit your full proposal package, visit the DSIP Portal.
SBIR|STTR Help Desk: usarmy.sbirsttr@army.mil
References: